1. Field of the Invention
The invention relates generally to interprocessor message exchange between devices attached through a bus and more specifically relates to methods and systems for performing such message exchange between a data consuming device and a data producing device coupled by a bus utilizing only write transactions on the bus (e.g., without issuing read transactions by either the consuming device or the producing device for such message exchanges).
2. Discussion of Related Art
In electronics and computing systems, devices are typically coupled to one another through shared bus structures. The peripheral component interconnect (PCI) bus standards have become a popular choice for designing of such interconnecting us structures. Other well-known, commercially available bus structures are also popular such as the AMBA AHB bus structure and numerous other well-known bus structures.
Many applications couple processors through such a shared bus structure such that the processors exchange messages to coordinate their respective operations. For example, some peripheral controller devices now incorporate multiple processors coupled to one another through a bus and adapted to exchange messages using low level bus transactions. Such systems help reduce the overhead processing associated with higher level data exchanges through more complex protocols. A first processor may perform, for example, processing related to control of the peripheral device while a second processor may provide higher level application functions for interfacing to external systems attached to the multi-processor controller system.
In such applications, the producer device (e.g., a first processor) may transfer a message to the consumer device (e.g., a second processor) through the interconnecting bus structure. In general, such bus structures may provide for low level read transactions as well as low level write transactions. The producing device typically requires information from the consuming device identifying a location in which the message to be transferred may be stored in the data memory of the consuming device. In the PCI bus structure as in most such bus structures, a device requiring information may request retrieval of such information from the other device using a read transaction and then await the return of the requested information in a read response transaction from the other device. As generally practiced in the art at present, a message consuming device may provide information to a message producing device through the shared bus structure. The read transaction from the message producing device requests an address in the data memory of the message consuming device for storing the message to be transferred. The read transaction is then completed by a subsequent read response transaction on the same bus to provide the requested information to allow a message transfer from the producing device to the consuming device.
In general, as presently practiced in the art, the processing of a read transaction and a corresponding subsequent read response transaction over the bus may cause the consuming device to experience idle periods of processing where the devices are, for practical purposes, “tied up” between the initiation of the read transaction and the eventual read response transaction to get the required address for transfer of the message. Though such idle time is not required by the PCI bus specifications nor most other standardized bus structures, the typical structure of present day bus interface circuit designs as applied to interprocessor message exchange between a consuming and producing device over the particular bus typically imposes such idle periods of processing. By contrast, most present day interprocessor message exchange designs tend to indicate immediate completion of a write transaction for transfer of data between a producing device and a consuming device. Therefore, read transaction processing on a typical bus is more costly than write transaction processing as measured by the degree of utilization of the processor for the devices involved in the message exchange.
It is evident from the above discussion that an ongoing need exists for improving processor utilization in the processing of message exchanges between producing and consuming devices coupled through shared bus structure.